CV

 

KATHERINE PARRY
225 Sycamore Ave #203 Vermillion, SD 57069
Phone: (605) 390-2570
me@KatherineParry.com   or    kparry@andrew.cmu.edu
________________________________________________________________________________________________

INTERNSHIPS:
Jan 2021-present    RISC-V Design Project in conjunction with Prof. David Harris of Harvey Mudd College and Prof. James Stine’s   VLSI
                                    Research Laboratory of Oklahoma State University. Responsible for the Floating-Point Unit (FPU) and its compliance to
                                    IEEE-754 Floating-Point standard.
                                             The FPU began with a Fused Multiplier-Adder (FMA). Currently, finishing up with a Radix-4 SRT Divider.
                                    Using Synopsys to determine how many instantiations can be accomplished in a single clock cycle.
                                    Synopsys is used for timing and optimization.
                                             During the school year, work is done during weekends and available time along with weekly Zoom meetings and
                                    full-time during the summer and winter breaks.
                                             Became experienced in IEEE-754 compliance and passing testFloat test vectors. Found an error in the shifting of 
                                    subnormals in The Handbook of Floating-Point Arithmetic and author Dr. Jean-Michel Mueller says a mention is
                                    expected in the next edition.


Sept-Dec 2019          High-Performance parallel networks between Cache and DDR memory. Invited by Prof. Paulo Ienne to
                                     intern at the Processor Architecture Laboratory at EPFL University (Lausanne, Switzerland). Hardware development
                                     using Chisel3. Also created code to analyze network performance following methodology learned in
                                     Interconnection Networks by Dr. William Dally.

 

NOTABLE ACCOMPLISHMENTS & HONORS:

  • Carnegie Mellon University Dean’s List with a 4.0 GPA.
  • Clay-Wolkin Fellow. Two years designing a RISC-V processor.
  • At age 17, co-reviewed paper submitted to IEEE Transactions on Computers. Paper titled: Hardware-Oriented Algorithm for Cube Root Calculation.
  • At age 16, invited to do research at EPFL in Switzerland. Worked on DDR memory to cache parallel Network-on-Chip (NoC).
  • At age 16, invited to speak in Kyoto, Japan, at the ARITH Computational Arithmetic Symposium on discovering an optimized squarer.
  • At age 12 received a top score on my AP Computer Science test.

AREAS OF PARTICULAR INTEREST:

    • Computational Arithmetic – I believe mathematics will change as new computational methods become mainstream. Today’s
      algorithms, such as machine learning’s gradient descent, are very sum-of-square intensive, yet being computed with larger, slower multipliers. 
    • Computer Architecture – especially massively parallel architectures such as used in GPUs
    • Application-Specific Computer Architectures
    • Network-on-Chips (NoC)
    • Three-dimensional Chip Architectures
    • Wafer based chips

EDUCATION
Aug 2021-present    Carnegie Mellon University Majors: Computer Architecture (ECE) & Physics
Dec-Mar 2020          Harvey Mudd College – Advanced Computer Architecture
Sept-Dec 2019          EPFL University (Lausanne, Switzerland) Master’s class on Cadence & Synopsys
2018 – 2020              South Dakota School of Mines & Technology – Computer Engineering & Mathematics

INTERNATIONAL

IEEE Transactions on Computers                                                                                                                           April 2020
               Co-paper reviewer with Prof. David Matula, the paper
                          “Hardware-Oriented Algorithm for Cube Root Calculation.”

Internship in Processor Architecture Laboratory; EPFL University                                                        Sept-Dec 2019
               A position typically reserved for Upper-division and Masters Students

High-Performance Computer Architecture conference (HPCA 2020)                                                   February 2020
                San Diego, California

ARITH 26 symposium speaker; Kyoto, Japan                                                                                               Summer 2019
               Speaker – Invited to present my research in Computational Arithmetic
                                  on optimizing the computation of a square.

RELEVANT SKILLS AND MEMBERSHIPS

  • Programming ability in Verilog, VHDL, Chisel, Scala, C/C++, Python, JAVA, and HTML.
  • Experienced using EDA tools Quartus, Vivado, ModelSim, Cadence, and Synopsys
  • Member of IEEE (Institute of Electrical & Electronics Engineers) Membership #95466989
  • Member of ACM (Association of Computing Machinery) Membership #2444592
  • Operating Systems: Linux & Windows
  • Graphic Illustration: Adobe Illustrator 
  • Self-studied the following subjects using Coursera and other resources:
    • Computational Arithmetic (Yamin Le)
    • Machine Learning (Andrew Ng)
    • General-Purpose Graphics Processor Architectures (Aamodt)
    • Interconnection Networks (Dally)
    • A Primer on Memory Consistency and Cache Coherence (Sorin)
    • On-Chip Networks (Jerger)
    • CMOS/VLSI (Weste)
    • Computer Architecture (Patterson & Hennessy)