{"id":48,"date":"2020-03-13T17:23:46","date_gmt":"2020-03-13T09:23:46","guid":{"rendered":"http:\/\/www.katherineparry.com\/?page_id=48"},"modified":"2022-07-13T22:05:25","modified_gmt":"2022-07-13T14:05:25","slug":"cv","status":"publish","type":"page","link":"http:\/\/www.katherineparry.com\/cv\/","title":{"rendered":"CV"},"content":{"rendered":"\r\n

 <\/p>\r\n\r\n\r\n\r\n

KATHERINE PARRY<\/strong>
225 Sycamore Ave #203 Vermillion, SD 57069
Phone: (605) 390-2570
me@KatherineParry.com\u00a0 \u00a0or\u00a0 \u00a0 kparry@andrew.cmu.edu
________________________________________________________________________________________________<\/p>\r\n\r\n\r\n\r\n

INTERNSHIPS:<\/strong><\/span>
Jan 2021-present\u00a0 \u00a0 RISC-V Design Project <\/strong>in conjunction with Prof. David Harris of Harvey Mudd College and Prof. James Stine’s\u00a0 \u00a0VLSI
\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 Research Laboratory of Oklahoma State University. Responsible for the Floating-Point Unit (FPU) and its compliance to
\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 IEEE-754 Floating-Point standard.
\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0The FPU began with a Fused Multiplier-Adder (FMA). Currently, finishing up with a Radix-4 SRT Divider.
\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 Using Synopsys to determine how many instantiations can be accomplished in a single clock cycle.
\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 Synopsys is used for timing and optimization.
\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0During the school year, work is done during weekends and available time along with weekly Zoom meetings and
\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 full-time during the summer and winter breaks.
\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0Became experienced in IEEE-754 compliance and passing testFloat test vectors. Found an error in the shifting of\u00a0
\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 subnormals in The Handbook of Floating-Point Arithmetic<\/em> and author Dr. Jean-Michel Mueller says a mention is
\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 expected in the next edition.<\/p>\r\n


Sept-Dec 2019\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 High-Performance parallel networks <\/strong>between Cache and DDR memory. <\/strong>Invited by Prof. Paulo Ienne to
\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0intern at the Processor Architecture Laboratory at EPFL University (Lausanne, Switzerland). Hardware development
\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0using Chisel3. Also created code to analyze network performance following methodology learned in
\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0Interconnection Networks<\/em> by Dr. William Dally.
<\/strong><\/p>\r\n

 <\/p>\r\n\r\n\r\n\r\n

NOTABLE ACCOMPLISHMENTS & HONORS:<\/strong><\/span><\/p>\r\n\r\n\r\n\r\n

    \r\n
  • Carnegie Mellon University Dean’s List with a 4.0 GPA.<\/li>\r\n
  • Clay-Wolkin Fellow. Two years designing a RISC-V processor.<\/li>\r\n
  • At age 17, co-reviewed paper submitted to IEEE Transactions on Computers. Paper titled: Hardware-Oriented Algorithm for Cube Root Calculation.<\/em><\/li>\r\n
  • At age 16, invited to do research at EPFL<\/a> in Switzerland. Worked on DDR memory to cache parallel Network-on-Chip (NoC).<\/li>\r\n
  • At age 16, invited to speak in Kyoto, Japan, at the ARITH<\/a> Computational Arithmetic Symposium on discovering an optimized squarer.<\/li>\r\n
  • At age 12 received a top score on my AP Computer Science test.<\/li>\r\n<\/ul>\r\n\r\n\r\n\r\n

    AREAS OF PARTICULAR INTEREST:<\/b><\/span><\/p>\r\n

      \r\n
    • \r\n
        \r\n
      • Computational Arithmetic – I believe mathematics will change as new computational methods become mainstream. Today’s
        algorithms, such as machine learning’s gradient descent, are very sum-of-square intensive, yet being computed with larger, slower multipliers.\u00a0<\/li>\r\n
      • Computer Architecture – especially massively parallel architectures such as used in GPUs<\/li>\r\n
      • Application-Specific Computer Architectures<\/li>\r\n
      • Network-on-Chips (NoC)<\/li>\r\n
      • Three-dimensional Chip Architectures<\/li>\r\n
      • Wafer based chips<\/li>\r\n<\/ul>\r\n<\/li>\r\n<\/ul>\r\n\r\n\r\n\r\n

        EDUCATION<\/strong><\/span>
        Aug 2021-present\u00a0 \u00a0 Carnegie Mellon University<\/strong> Majors: Computer Architecture (ECE) & Physics
        Dec-Mar 2020\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 Harvey Mudd College – <\/strong>Advanced Computer Architecture
        <\/strong>Sept-Dec 2019\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 EPFL University <\/strong>(Lausanne, Switzerland) <\/strong>Master’s class on Cadence & Synopsys
        <\/strong>2018 – 2020\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 South Dakota School of Mines & Technology – <\/strong><\/strong>Computer Engineering & Mathematics
        <\/strong><\/p>\r\n\r\n\r\n\r\n

        INTERNATIONAL<\/strong><\/span><\/p>\r\n\r\n\r\n\r\n

        IEEE Transactions on Computers<\/em>\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0April 2020
        \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0Co-paper reviewer with Prof. David Matula, the paper
        \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 “Hardware-Oriented Algorithm for Cube Root Calculation.”<\/p>\r\n

        Internship in Processor Architecture Laboratory<\/em>; EPFL University\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 Sept-Dec 2019
        \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0A position typically reserved for Upper-division and Masters Students<\/p>\r\n

        High-Performance Computer Architecture<\/em> conference (HPCA 2020)<\/em>\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0February 2020
        \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 San Diego, California<\/p>\r\n

        ARITH 26 symposium<\/a> speaker; Kyoto, Japan<\/em>\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0Summer 2019
        \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0Speaker – Invited to present my research in Computational Arithmetic
        \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 on optimizing the computation of a square.<\/p>\r\n\r\n\r\n\r\n

        RELEVANT SKILLS AND MEMBERSHIPS<\/strong><\/span><\/p>\r\n\r\n\r\n\r\n

          \r\n
        • Programming ability in Verilog, VHDL, Chisel, Scala, C\/C++, Python, JAVA, and HTML.<\/li>\r\n
        • Experienced using EDA tools Quartus, Vivado, ModelSim, Cadence, and Synopsys<\/li>\r\n
        • Member of IEEE (Institute of Electrical & Electronics Engineers) Membership #95466989<\/li>\r\n
        • Member of ACM (Association of Computing Machinery) Membership #2444592<\/li>\r\n
        • Operating Systems: Linux & Windows<\/li>\r\n
        • Graphic Illustration: Adobe Illustrator\u00a0<\/li>\r\n
        • Self-studied the following subjects using Coursera and other resources:
          \r\n
            \r\n
          • Computational Arithmetic (Yamin Le)<\/li>\r\n
          • Machine Learning (Andrew Ng)<\/li>\r\n
          • General-Purpose Graphics Processor Architectures (Aamodt)<\/li>\r\n
          • Interconnection Networks (Dally)<\/li>\r\n
          • A Primer on Memory Consistency and Cache Coherence (Sorin)<\/li>\r\n
          • On-Chip Networks (Jerger)<\/li>\r\n
          • CMOS\/VLSI (Weste)<\/li>\r\n
          • Computer Architecture (Patterson & Hennessy)<\/li>\r\n<\/ul>\r\n<\/li>\r\n<\/ul>\r\n","protected":false},"excerpt":{"rendered":"

              KATHERINE PARRY225 Sycamore Ave #203 Vermillion, SD 57069Phone: (605) 390-2570me@KatherineParry.com\u00a0 \u00a0or\u00a0 \u00a0 kparry@andrew.cmu.edu________________________________________________________________________________________________ INTERNSHIPS:Jan 2021-present\u00a0 \u00a0 RISC-V Design Project in conjunction with Prof. David…<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":[],"_links":{"self":[{"href":"http:\/\/www.katherineparry.com\/wp-json\/wp\/v2\/pages\/48"}],"collection":[{"href":"http:\/\/www.katherineparry.com\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"http:\/\/www.katherineparry.com\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"http:\/\/www.katherineparry.com\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.katherineparry.com\/wp-json\/wp\/v2\/comments?post=48"}],"version-history":[{"count":132,"href":"http:\/\/www.katherineparry.com\/wp-json\/wp\/v2\/pages\/48\/revisions"}],"predecessor-version":[{"id":4343,"href":"http:\/\/www.katherineparry.com\/wp-json\/wp\/v2\/pages\/48\/revisions\/4343"}],"wp:attachment":[{"href":"http:\/\/www.katherineparry.com\/wp-json\/wp\/v2\/media?parent=48"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}} Katherine Parry Skip to content

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